UBoot. In AM335x the ROM code serves as the bootstrap loader, sometimes referred to as the Initial Program Loader IPL or the Primary Program Loader PPL. This PCI Serial Card adds two highspeed 9pin serial COM ports to any PCI equipped PC. A Serial PCI card is the easiest way to create a real COM port in your computer. AM3. 35x U Boot Users Guide Texas Instruments Wiki. AM3. 35x U Boot Users Guide. Linux PSPU Boot. Serial Number Criteria Description Criteria B17G Data last updated Tue Mar 15 092504 2016 4124440. Boeing B17F10BO Fortress MSN 31253174 24440. SetUp_VM/SetUp_13.jpg' alt='Sd Card Serial Number Windows 7' title='Sd Card Serial Number Windows 7' />In AM3. ROM code serves as the bootstrap loader, sometimes referred to as the Initial Program Loader IPL or the Primary Program Loader PPL. The booting is completed in two consecutive stages by U Boot binaries. The binary for the 1st U Boot stage is referred to as the Secondary Program Loader SPL or the MLO. The binary for the 2nd U Boot stage is simply referred to as U Boot. SPL is a non interactive loader and is a specially built version of U Boot. It is built concurrently when building U Boot. The ROM code can load the SPL image from any of the following devices. Memory devices non XIP NANDSDMMCThe image should have the Image header. The image header is of length 8 byte which has the load addressEntry point and the size of the image to be copied. RBL would copy the image, whose size is given by the length field in the image header, from the device and loads into the internal memory address specified in the load address field of Image header. Peripheral devices UARTRBL loads the image to the internal memory address 0x. No Image Header present. Two stage U Boot design. This section gives an overview of the two stage U Boot approach adopted for AM3. X. The size of the internal RAM in AM3. X is 1. 28. KB out of which 1. KB at the end is used by the ROM code. Also, 1 KB at the start 0x. This places a limit of 1. KB on the size of the U Boot binary which the ROM code can transfer to the internal RAM and use as an initial stack before initialization of DRAM. Since it is not possible to squeeze in all the functionality that is normally expected from U Boot in lt 1. KB after setting aside some space for stack, heap etc a two stage approach has been adopted. Initial stage initalize only the required boot devices NAND, MMC, I2. C etc 2nd full stage initall all other devices ethernet, timers, clocks etc. The 1st binary is generated MLO and the 2nd stage is generated as u boot. NOTEWhen using memory boot NAND a header needs to be attached to the SPL binary indicating the load address and the size of the image. SPI boot additionally requires endian conversion before flashing the image. When using peripheral boot UART there can be no header as the load address is fixed. Updated Toolchain. Starting with Sitara Linux SDK 6. ARM 9 devices a new Linaro based toolchain will be used. Details about the change in toolchain location can be found here. Also details about the switch to Linaro can be found here. AM1. 8x users are not affected by the switch to Linaro. Therefore, any references to the Linaro toolchain prefix arm linux gnueabihf should be replaced with arm arago linux gnueabi. Building U Boot. Prerequisite. GNU toolchain for ARM processors from Arago is recommended. Arago Toolchain can be found in the linux devkit directory of the SDK here. NOTEBelow steps assumes that the release package is extracted inside directory represented as AM3. PSP DIRChange to the base of the U Boot directory. AM3. 35x LINUX PSP MM. MM. mm. pp. bb. Building into a separate object directory with the O parameter to make is strongly recommended. Commands d. am. Oam. CROSSCOMPILEarm linux gnueabihf ARCHarm am. This will generate two binaries in the am. MLO and u boot. img along with other intermediate binaries that may be needed in some cases see below. Host configuration. At&Amp;T Wireless Activation here. Serial port configuration. Connect a serial cable from the serial port of the EVM serial port is next to the power switch to the COM port on either the Windows machine or Linux host depending on where youll be running the serial terminal software. For correct operation the serial terminal software should be configured with the following settings. Baud rate 1. 15,2. Flow control None. NOTEIf Teraterm is being used, ensure that the latest version 4. Teraterm is installed. The implementation of the Kermit protocol in Teraterm is not reliable in older versions. The latest version of Teraterm 4. Recent Teraterm updates causes slow Binary transfer over UART. In such cases, use Windows in built Hyper. Terminal application. Target configuration. Boot Switch Settings. This option is only available on Am. EVM. Switch SW3 is for selecting the boot modes. Also, separate DIP switch SW8 is provided to select various profiles on EVMs. The picture below shows the boot mode configuration switch SW3 on the AM3. X EVM. RED circle shows OFF and GREEN circles shows ON switches. IMPORTANTON is labeled on the wrong side of SW3 boot mode switch. NOTEThe bootmode setting in this picture is for NAND boot. NAND boot corresponds to SW3 5 1 1. Make sure that the EVM boot switch settings are set to required boot mode and then power on the board. NANDIn order to boot from the NAND flash, set the SW3 switch as follows Dip switch. SPIIn order to boot from the SPI flash, set the SW3 switch as follows Dip switch. USBIn order to boot from the USBmode, set the SW3 switch as follows Dip switch. UARTIn order to boot from the UART mode, set the SW3 switch as follows Dip switch. SDIn order to boot from the SD card, set the SW3 switch as follows Dip switch. CPSW Ethernet. In order to boot from the CPSW ethernet mode, set the SW3 switch as follows Dip switch. NOTEThe setting of switch SW3 7 6 is because the EVM uses RGMII mode. For more details please refer to the TRM. NOTEDue to heavy pin muxing, boot device is selectively available on selected AM3. EVMs profiles. Details about the availability of the peripherals on different Profiles can be found from the EVM reference manual. Flashing U Boot with CCSNOTEBoth the stages of U Boot need to be flashed on the same media. The tools are provided in the PSP release to write SPL U Boot on to the NAND flashfor NAND boot. Refer to AM3. 35x Flashing Tools Guide wiki page for instructions on how to flash the pre built or compiled binary to NAND flash or the recompiled one with the help of the NAND flash writer. After flashing the 2 stages, make sure boot mode is set to NAND and power on the board. Boot Modes. NANDNOTEhe following sub sections illustrate the usage of NAND specific commands on AM3. X EVM. Refer to EVM Switch Settings section for more info on enablingdisabling different boot devices. This section gives an overview of the NAND support in U Boot. It also describe how to store the kernel image, RAMDISK or the UBIFS filesystem to NAND so as to have a network free boot right from powering on the board to getting the kernel up and running. Overview. Micron NAND parts page size 2. KB, block size 1. KB are supported on AM3. XEVM platforms. NAND Layout. The NAND part on the EVM has been configured in the following manner. The addresses mentioned here are used in the subsequent NAND related commands. SPL start SPL copy on 1st block. FFFF SPL end. SPL. SPL copy on 2nd block. FFFF SPL. backup. SPL. backup. 2 start SPL copy on 3rd block. FFFF SPL. backup. SPL. backup. 3 start SPL copy on 4th block. FFFF SPL. backup. U Boot start. . BFFFF U Boot end. ENV start. 0x. FFFF ENV end. Linux Kernel start. FFFF Linux Kernel end. File system start. NAND end Free end. Writing to NANDTo write len bytes of data from a memory buffer located at addr to the NAND block offset. U Boot nand write lt addr lt offset lt len. NOTEffset  len fields should be in align with 0x.